Method and apparatus for address transfers, system serialization, and centralized cache and transaction control, in a symetric multiprocessor system
US6466825B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2001 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Aug 10, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0822
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A preferred embodiment of a symmetric multiprocessor system includes a switched fabric (switch matrix) for data transfers that provides multiple concurrent buses that enable greatly increased bandwidth between processors and shared memory. A Transaction Controller, Transaction Bus, and Transaction Status Bus are used for serialization, centralized cache control, and highly pipelined address transfers. The shared Transaction Controller serializes transaction requests from Initiator devices that can include CPU/Cache modules and Peripheral Bus modules. The Transaction Bus of an illustrative embodiment is implemented using segmented buses, distributed muxes, point-to-point wiring, and supports transaction processing at a rate of one transaction per clock cycle. The Transaction Controller monitors the Transaction Bus, maintains a set of duplicate cache-tags for all CPU/Cache modules, maps addresses to Target devices, performs centralized cache control for all CPU/Cache modules, filters unnecessary Cache transactions, and routes necessary transactions to Target devices over the Transaction Status Bus. The Transaction Status Bus includes both bus-based based and point-to-point control of…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.