Method and apparatus for performing a sum-and-compare operation
US6466960B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 13, 1999 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | May 13, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/4991
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus are provided for performing a fast sum-and-compare operation. The apparatus of the present invention utilizes a single carry save adder in conjunction with a zero detect circuit for performing logic operations to determine whether or not the sum of a plurality of operands is equal to one or more constants. The Carry Save Adder generates a sum, M, and carry, L, that are output from the carry save adder to the zero detect circuit. The zero detect circuit produces internal carry signals that are passed between adjacent bit-cells of the zero detect circuit. The zero detect circuit generates outputs Zk1 through Zkn which are true if the condition A+B+C={k1, k2, k3 . . . kn} for all constants k1 through kn. The carry signals propagate through only one bit of the zero detect circuit, thereby providing the sum-and-compare circuit of the present invention with extremely high speed. The constants are programmed into the metal mask of the zero detect circuit, thereby allowing a single circuit design to be used for multiple values of the constant k.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.