Apparatus, method and system for using cache memory as fail-over memory
US6467048B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 1999 |
| Grant date | Oct 15, 2002 |
| Priority date | — |
| Expiry date | Oct 7, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system having a main memory and a cache memory, the computer system uses portions of the cache memory to store information from defective main memory locations until the main memory can be repaired. The address space of the main memory is always maintained by substituting cache-lines of cache memory for the defective main memory locations. A fail-over memory status bit in the cache memory controller indicates when a cache line of the cache memory contains fail-over information from the defective or failing main memory so that that cache-line will not be written over by a cache replacement algorithm. When the fail-over status bit is set, the contents of the fail-over memory location(s) remains in the cache-line and all memory reads and writes are directed to only that cache-line of the cache memory and not the main memory for the fail-over memory location(s). Also no write-back of the fail-over memory location(s) from cache memory to the main memory is required nor desired until the main memory location is repaired or replaced. Indicator lights may be used to represent the different activities of the main and cache memories at detection of the defective memory location, d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.