Method for manufacturing chip capacitor
US6467142B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2000 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | May 25, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49798
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A terminal frame including plural pairs of terminal sections arranged in rows and columns is prepared. Each pair includes a flat anode terminal section and a flat cathode terminal section disposed in the same plane with their tip ends being spaced from and facing each other. Plural capacitor elements are prepared. Each capacitor element has a cathode layer on substantially entire outer surface thereof, and a tantalum lead. The capacitor elements are placed on the frame. The tantalum lead of each capacitor element is coupled to one major surface of the anode terminal section of one pair of terminal sections, with the cathode layer of that capacitor element coupled to one major surface of the cathode terminal section of the same pair. The frame with the capacitor elements mounted thereon are coated with resin in such a manner that all of the capacitor elements are encapsulated in the resin, while at least a portion of the opposite major surface of each anode terminal section and at least a portion of the opposite major surface of each cathode terminal section are left exposed. After that, the frame and the resin encapsulation are cut to separate the capacitor elements with the anode …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.