Method of fabricating a high-voltage transistor
US6468847B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2000 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Nov 27, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.