Method of fabricating electrically isolated double gated transistor
US6468848B1 · kind B1 · utility
12Cited by
8References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 10, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | May 10, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A gated field effect transistor (gated-FET) in which the body of the FET is electrically isolated from the substrate thereby reducing leakage current through parasitic bipolar action. The back-bias of the channel of the FET is jointly controlled by a diode coupled with a capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.