Semiconductor device and method of fabricating the same
US6469317B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 16, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Dec 16, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
Abstract
The purpose of the present invention is to provide a reliable semiconductor device comprising TFTs having a large area integrated circuit with low wiring resistance. One of the features of the present invention is that an LDD region including a region which overlaps with a gate electrode and a region which does not overlap with the gate electrode is provided in one TFT. Another feature of the present invention is that gate electrode comprises a first conductive layer and a second conductive layer and portion of the gate wiring has a clad structure comprising the first conductive layer and the second conductive layer with a low resistance layer interposed therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.