Semiconductor memory device having different distances between gate electrode layers
US6469356B2 · kind B2 · utility
12Cited by
5References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Jun 8, 2021 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
The invention provides SRAMs that can reduce memory cells in size and correct light proximity effect. Gate electrode layers in a first layer, drain-drain connection layers in a second layer, and drain-gate connection layers in a third layer define conduction layers of a flip-flop. A source contact layer of load transistors are located adjacent end sections of the gate electrode layers, and both of the end sections bend outwardly to avoid contact with the source contact layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.