Method and device for providing symetrical monitoring of ESD testing an integrated circuit
US6469536B1 · kind B1 · utility
4Cited by
4References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 17, 2000 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Nov 17, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and a device (4) for testing an integrated circuit (DUT) uses a stress signal and surface monitoring. A stress signal generator (5) is connected to the integrated circuit (DUT) to apply the stress signal (v(t)) to the integrated circuit. A failure is observed in real time by monitoring the surface (6) of the integrated circuit (DUT) during a monitoring time window (&Dgr;T) by an emission microscope (10) having a controllable shutter (15). The time window has a predetermined relation with respect to the duration of the stress signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.