Pre-charging circuit of an output buffer
US6469566B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Jan 31, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pre-charging circuit for the output node of an output buffer of an integrated digital system generates a first pulse for enabling the output of new data and a second pulse having a shorter duration than the first pulse for loading the new data in an output data register. The output data register is coupled to the input of the output buffer. A capacitor is connected in parallel to the load capacitance of the output node of the buffer by a pass-gate. The pass-gate is enabled by a pre-charge command corresponding to the logic AND of the second pulse and of the logic XOR of the new data and the data currently present on the output node. A driver is disabled by the first pulse for charging the capacitor to a voltage corresponding to the logic level of data belonging to the group that includes the new data and a logic inversion of the current data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.