Cache addressing
US6469705B1 · kind B1 · utility
3Cited by
4References
29Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 21, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Sep 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/653
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system, main memory is accessed via a cache. Locations in a main memory are accessed by a process with reference to addresses. Each address comprises virtual bits and physical address bits. Selected bits of the physical address bits identify areas in the cache. Permutations of the selected bits are used to identify buffer alignments in main memory, in response to an identification of requirements for the process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.