Internal protection circuit and method for on chip programmable poly fuses
US6469884B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Dec 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (10) having at least one programmable fuse (F1) and ESD circuitry (MN3, MN1) preventing the fuse (F1) from being unintentionally blown when a voltage transient exists on a main voltage potential (Vmain). The ESD circuitry preferably comprises of MOSFET switches which are coupled to turn on quicker than a main fuse programming switch (MNmain) due to the voltage transient, thereby insuring that the main switch remains off during the voltage transient to prevent the unintentional blowing of the fuse F1. The circuit is well suited for programmable logic device (PLDs), allowing for read voltages as low as 6 volts, and allowing for programming voltages as high as 40 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.