Memory cell with improved retention time
US6469925B1 · kind B1 · utility
7Cited by
4References
20Claims
0Family size
Inventor
Key dates
| Filing date | May 14, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | May 14, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/05
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory cell having first and second access transistors coupled to a storage transistor is disclosed. A boosted voltage is coupled to the gate of the storage transistor to increase the charge stored in the memory cell, thereby improving retention time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.