Semiconductor memory device having regions with independent word lines alternately selected for refresh operation
US6469947B2 · kind B2 · utility
4Cited by
15References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 2, 2001 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | May 2, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided to reduce current consumption during a refresh operation by decreasing the number of wordlines activated at the same time, including a block set having a plurality of cell array blocks which are divided into a plurality of regions which employ wordlines independently from each other, row driving circuit to alternatively select the wordlines arranged each in the regions, and column driving circuit to activate columns of the cell arrays involved in the wordlines selected by the row driving circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.