Computer network switch with parallel access shared memory architecture
US6470021B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 5, 1998 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Oct 5, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/351
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A packet switch includes a multiple of bidirectional ports that are each connected by dedicated signal paths to a multiple of memory subsystems that in turn are connected to shared memory within the switch. The signal path from each port carries a fragment of a data stream between the port and each memory subsystem. The ports send and receive data stream fragments in parallel from the memory subsystems. This parallel action reduces the bandwidth required of a memory subsystem by dividing the port's data stream among the multiple memory subsystems. In storing data for forwarding to another port, each memory subsystem selects on a time division basis in parallel the data stream fragments from the same port and stores them in memory. In retrieving data from memory for a port, each memory subsystem selects on a time division basis in parallel the same port to receive the data stream fragments read from memory. The bit width of the signal paths between the ports and memory subsystems is reduced by sending smaller, individual data stream fragments between ports and memory subsystems and sending larger, aggregate data stream fragments between memory subsystems and memory. Within each memo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.