Method and architecture for complex datapath decimation and channel filtering
US6470365B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 23, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Aug 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2218/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A decimation and channel filter (100 or 23) in an oversampled system includes a combined decimation and channel filtering architecture for simultaneously processing in-phase and quadrature phase complex input signals. A decimation filter (24) of the combined decimation and channel filter provides sampled outputs to a memory (108) to provide an intermediate result (604), which is stored in the memory (108) in a first format (608). A channel filter (26) of the combined decimation and channel filter processes (610) a decimation final result of the decimation filter in a second format in the memory to provide a final result. This architecture minimizes cost and current drain in a complex signal path decimation and channel filtering process. In addition, a channel filtering algorithm is used to ideally minimize current drain by a factor of 2.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.