Apparatus and method for delivering interrupts via an APIC bus to IA-32 processors
US6470408B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Apr 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and a method are provided to distribute interrupts from a system bus to Intel® Architecture (IA)-32 applications processors. The apparatus includes a bridge that couples a processor bus to the system bus. In addition, the bridge is coupled to an advanced programmable interrupt controller (APIC) by an APIC bus. The bridge monitors the system bus for interrupts and converts selected interrupt transactions into APIC messages. The bridge then sends the APIC messages to the APIC bus. Each of the applications processors is also coupled to one of many APIC buses. The applications processor that is the target of the interrupt transaction receives the APIC message and executes an interrupt handler routine. The apparatus and method also incorporate interrupt transaction buffering and throttling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.