Emulation of next generation DRAM technology
US6470417B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 12, 2000 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Apr 7, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A current generation, quad RAS, single CAS, stacked component (101) including four 4 Mb×4 bits 11/11 DRAMs (210-213) is arranged to emulate a next generation 16 Mb×4 bits 12/12 DRAM. The (24) bit address signal provided by memory controller (105) includes a row address of 12 bits and a column address of 12 bits. Each DRAM (210-213) within the current generation DRAM component (101) requires only 11 row address bits and 11 column address bits. The additional 1 row address bit and 1 column address bit are provided to decoder logic (103). The additional row address bit is decoded by the decoding logic (103) to direct the RAS signals over two of the four RAS lines (201-204), thereby activating the two signaled DRAMs. The additional column address bit is then decoded by decoding logic (103) to de-activate one of the two signaled DRAMs , leaving only one DRAM activated. CAS line (205) directs the CAS signal to all of the stacked DRAMs (210-213). The combination of both RAS and CAS is provided to only one of the plurality of current generation DRAMs, thereby permitting access to that particular current generation DRAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.