Pipelining a content addressable memory cell array for low-power operation
US6470418B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Jan 15, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1039
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A content addressable memory (CAM) system that includes first and second CAM arrays, which generate first and second sets of match control signals, respectively, having higher and lower priorities, respectively. The first CAM array is enabled during a first memory cycle, and the first set of match control signals are analyzed. If a match exists in the first CAM array, a first priority encoder is enabled to process the first set of match control signals. If no match exists, the first priority encoder is not enabled, and a second memory cycle is initiated. The second CAM array is enabled during the second memory cycle, and the second set of signals is analyzed. If a match exists in the second CAM array, a second priority encoder is enabled to process the second set of match control signals. If no match exists, the second priority encoder is not enabled.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.