Sequential memory access cache controller
US6470428B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Jun 26, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache controller is disclosed that includes a first means for determining when data specified by a memory address requested by the processor is absent from the cache, and a second means for determining when the processor reads sequential memory addresses. The second means is activated when the first means detects that data is absent from the cache and causes the cache controller to (i) permit data to be supplied from the main memory to the processor, even when the data is available in the cache; (ii) inhibit the first means from determining whether requested data is available in the cache; and (iii) update the cache with data supplied to the processor from the main memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.