Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information
US6470443B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2000 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Mar 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A multi-threaded processor comprising a pipeline including a number of stages processing instructions belonging to a plurality of threads. A buffer stores instructions from different ones of the threads. Count logic stores count information relating to each of the threads to indicate the number of instructions in each of the corresponding threads that have a particular attribute. A selection logic circuit has an output coupled to the buffer to determine which instruction is to be read from the buffer based on the count information stored by the count logic. The count information may, for example, provide information relating to a likelihood that one or more instructions belonging to each of the threads will be cancelled; relating to a count of unresolved branch instructions; or relating to a count of outstanding data cache misses. In operation, a thread may be selected for execution based on a selected attribute to enhance processing performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.