Method and system for data processing system self-synchronization
US6470458B1 · kind B1 · utility
25Cited by
3References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Jul 29, 1999 |
| Grant date | Oct 22, 2002 |
| Priority date | — |
| Expiry date | Jul 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for dynamic synchronization of a data processing system processor chips. One of a plurality of chips is designated as a primary chip and all other chips as secondary chips. The clock phase of the chips are synchronized utilizing the primary chip's clock phase as a reference clock phase for the secondary chips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.