Increased lateral oxidation rate of aluminum indium arsenide

US6472695B1 · kind B1 · utility

Assignee

• The Regents of the University of California · US

Inventors

• Eric M. Hall · Rochester Hills, US
• Larry A. Coldren · Lompoc, US

Key dates

• Filing date: Jun 15, 2000
• Grant date: Oct 29, 2002
• Expiry date: Jul 25, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01S5/3235
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The present invention discloses a device and a method for producing an oxidizable digital alloy that is sufficiently strain-compensated to provide for substantially defect-free growth on indium phosphide. The device comprises a layer of semiconductor material, a first layer, and a second layer. The first layer is indium arsenide and is coupled to the layer of semiconductor material, wherein the first layer of indium arsenide is under a compressive strain by a lattice mismatch between the layer of semiconductor material and the first layer of indium arsenide. The second layer is aluminum arsenide and is coupled to the layer of indium arsenide, wherein the second layer of aluminum arsenide is under a tensile strain by a lattice mismatch between the second layer and the first layer. The first layer and the second layer comprise a digital alloy of aluminum indium arsenide, and create a quasi-strain-compensated substantially defect-free alloy on the layer of semiconductor material therein. A superlattice period of the first layer of indium arsenide and a second layer of aluminum arsenide is selected to allow an oxide of desired depth to be produced from the digital alloy.