Semiconductor device with reduced transistor leakage current
US6472712B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1999 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jul 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76281
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device improved to suppress a leakage current of a transistor is provided. A gate electrode is disposed on a semiconductor substrate. A pair of p type source/drain layers are provided on the surface of the semiconductor substrate, on both sides of the gate electrode in the gate length direction Y. An n type gate width determining layer is provided on the surface of the semiconductor substrate to sandwich the source/drain layers in the width direction X of the gate electrode, which determines a gate width of the gate electrode. The source/drain layers and the gate width determining layer are isolated by PN junction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.