Reduced soft error rate (SER) construction for integrated circuit structures

US6472715B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventors

• Yauh-Ching Liu · Boise, US
• Helmut Puchner · Santa Clara, US
• Ruggero Castagnetti · Menlo Park, US
• Weiran Kong · Shanghai, CN
• Lee Phan · Fremont, US
• Franklin Duan · San Jose, US
• Steven Michael Peterson · Eagan, US

Key dates

• Filing date: Sep 28, 2000
• Grant date: Oct 29, 2002
• Expiry date: Sep 28, 2020

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0191

Abstract

An integrated circuit structures such as an SRAM construction wherein the soft error rate is reduced comprises an integrated circuit structure formed in a semiconductor substrate, wherein at least one N channel transistor is built in a P well adjacent to one or more deep N wells connected to the high voltage supply and the deep N wells extend from the surface of the substrate down into the substrate to a depth at least equal to that depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell. For a 0.25 &mgr;m SRAM design having one or more N wells of a conventional depth not exceeding about 0.5 &mgr;m, the depth at which alpha particle-generated electron-hole pairs can effectively cause a soft error in the SRAM cell is from 1 to 3 &mgr;m. The deep N well of the 0.25 &mgr;m SRAM design, therefore, extends down from the substrate surface a distance of at least about 1 &mgr;m, and preferably at least about 2 &mgr;m. In a preferred embodiment, the implantation of the substrate to form the deep N well of the improved SRAM of the invention is carried out in a manner which will cause straggle, i.e., cause the doped volume comprising the…