Self-referencing slicer method and apparatus for high-accuracy clock duty cycle generation
US6472918B1 · kind B1 · utility
19Cited by
7References
19Claims
0Family size
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Key dates
| Filing date | Aug 23, 1999 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Aug 23, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system and method for regulating the duty cycle of a digital clock signal derived from an oscillator signal. The oscillator signal is DC-biased to a DC value representing an average DC value of an ideal digital clock signal having a 50% duty cycle. The DC-biased oscillator signal is compared to a reference voltage. The digital clock signal is generated as a substantially square wave signal having first and second logic levels, and is generated in response to the comparison of the DC-biased oscillator signal and the reference voltage. The DC component of the generated digital clock signal is then used as the reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.