Tunable input trap circuit and image trap circuit
US6472956B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 24, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | May 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03J3/185
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An input trap circuit removes a predetermined frequency component included in an input signal and then outputs the input signal to a circuit at a later stage. The input trap circuit is provided with: a parallel oscillation circuit in which a pair of variable capacitance diodes are connected in series such that cathodes thereof are connected to each other at a junction portion and in which an inductance is connected in parallel to the variable capacitance diodes between anodes of the variable capacitance diodes at both ends thereof; a voltage applying device for applying a voltage to the junction portion so as to vary capacitance values of the variable capacitance diodes on the basis of reverse voltage characteristics of the variable capacitance diodes respectively; and a variable capacitor element connected between the junction portion and a ground.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.