Self burn-in circuit for semiconductor memory
US6473346B1 · kind B1 · utility
11Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 19, 1996 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jan 19, 2016 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved self burn-in circuit for a semiconductor memory generates a control signal, an address, and a test data for a burn-in test operation when a certain self burn-in test condition is satisfied. The burn-in circuit includes a burn-in detector for generating a control signal, an address signal, and a test data for a burn-in test operation when a self burn-in test condition is achieved. A memory array performs a burn-in test operation when the test data is written into and/or read from a memory cell which is selected by the address signal in accordance with the control signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.