Semiconductor memory device
US6473358B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2002 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Mar 15, 2022 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device has a column address decoder which includes first and second pre-decoders corresponding to high-order and low-order addresses, respectively, a shift register for using the output signal of the second pre-decoder as an initial value, and an output circuit for selecting either the output signal of the second pre-decoder or the output signal of the shift register in accordance with an action mode. The select signal is formed by the output signal of the first pre-decoder and the output signal through the output circuit. The shift register includes a first shift register for an even address and a second shift register for an odd address and forms two sets of continuous select signals of the bit lines, as composed of a sequential action and an interleave action, on the basis of the initial value by combining its up and down shifting actions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.