Method and apparatus for providing deterministic resets for clock divider systems
US6473476B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 6, 1999 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Jan 6, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock divider system with reset synchronization includes a divider circuit, a synchronizer circuit, and a synchronous delay circuit. The divider circuit has a clock input, a divider reset input, and a divided clock output. The synchronizer has a clock input, and a synchronous reset input, and a synchronized reset output having an active edge aligned with an active edge of the clock. The synchronous delay circuit has a clock input and a synchronized reset input coupled to the synchronized reset output of the synchronizer, and an output coupled to the divider reset input of the divider. A method for providing reset synchronization for a clock divider system includes developing a reset synchronization signal aligned with an active edge of a clock after receiving an asynchronous reset signal, delaying the reset synchronization signal for at least one cycle to provide a delayed reset synchronization signal, and developing a clock divider reset signal from the delayed reset synchronization signal, that is aligned with an active edge of the clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.