Method and apparatus for prevent stalling of cache reads during return of multiple data words
US6473834B1 · kind B1 · utility
0Cited by
31References
6Claims
0Family size
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Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0859
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system comprising a first level cache, a second level cache, and a processor return path, wherein only one of the first level cache and second level cache can control the processor return path at a given time, an improvement comprises a queue disposed between an output of the first level cache and the processor return path to buffer data output from the first level cache so that the first level cache can continue to process memory requests even though the second level cache has control of the processor return path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.