Computing system and cache memory control apparatus controlling prefetch in hierarchical cache memories
US6473836B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 25, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Feb 25, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0862
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache memory control apparatus provided to prevent necessary data from being ejected from hierarchical cache memories and to avoid conflicts of process in the main pipeline of a processing unit (arithmetic unit), even when prefetch commands are issued at high frequency. The apparatus includes a command control section to issue a prefetch command instruction that speculative data is to be fetched (prefetched) from a main storage unit into a plurality of hierarchically arranged cache memories, and a prefetch control section to changeably select at least one of the hierarchically arranged cache memories as a destination to receive prefetch data when the prefetch command issued from the command control section is executed, according to at least one of status information of one of the cache memories and a type or kind of prefetch. The apparatus is particularly useful when applied to a computer system of the type having a prefetch operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.