Digital circuit layout techniques using circuit decomposition and pin swapping
US6473885B1 · kind B1 · utility
25Cited by
7References
17Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/39
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique for analyzing digital circuits to identify pin swaps is provided for circuit layout and similar tasks in which the circuit is first decomposed into regions. Logic functions of the regions are decomposed into a directed graph of the logic functions. A swap structure is created in accordance with the directed graph to facilitate identification of input equivalences.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.