Clock circuit and method of designing the same
US6473890B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Sep 18, 2000 |
| Grant date | Oct 29, 2002 |
| Priority date | — |
| Expiry date | Feb 23, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Based on the arrangement of a plurality of synchronous devices in an integrated circuit or on timing constraints, a group of discrete clock delay values composed of a finite number of discrete values to be allocated as respective clock delay values to the individual synchronous devices is determined. Then, the clock delay value selected from the group of discrete clock delay values is allocated as a selected clock delay value to each of the synchronous devices, while the operation of the integrated circuit is ensured. Thereafter, a clock circuit for supplying a clock signal to each of the synchronous devices in accordance with the selected clock delay value is designed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.