Method for growing semiconductor layer and method for fabricating semiconductor light emitting elements
US6475820B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jun 15, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S2304/12
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present invention provides a method for growing a semiconductor layer by which the size of generable voids is controllable, inclination of the c-axis of the semiconductor crystal is avoidable and the defects in the semiconductor layer is reducible, in which a first semiconductor layer typically made of GaN is formed in a ridge pattern on a substrate, and a second semiconductor layer typically comprising GaN is then formed on the first semiconductor layer under a condition by which the growth rate in the direction parallel to the major plane of the substrate is larger than that in the direction perpendicular thereto, which is attainable by controlling the pressure in a reaction chamber in which the vapor-phase growth proceeds at 53,200 Pa (400 Torr) or above, to allow the side planes of the second semiconductor layer incline at an acute angle to the bottom plane thereof.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.