Semiconductor memory device
US6476424B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Feb 7, 2020 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S257/903
Abstract
A semiconductor memory device which can suppress the occurrence of corner rounding through the resist patterning process to achieve a reduction in cell size and higher integration. A relationship between a channel width DT.W of the drive transistor, a channel length DT.L of the drive transistor, a channel width WT.W of the word transistor and a channel length WT.L of the word transistor is given by: (DT.W/WT.W)/(WT.L/DT.L)<1.2. The channel width DT.W of the drive transistor is equal to the channel width WT.W of the word transistor, to reduce steps in the patterns of p-type active regions. The channel length WT.L of the word transistor is larger than the channel length DT.L of the drive transistor, that is, (WT.L/DT.L)>1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.