Semiconductor parallel tester
US6476628B1 · kind B1 · utility
27Cited by
9References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 28, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2889
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A semiconductor parallel tester is disclosed for simultaneously testing a plurality of DUTs secured to a handling apparatus. The test system includes a system controller for initiating system test signals and a pin electronics assembly responsive to the system test signals to generate test pattern signals for application to the plurality of DUTs. The system further includes a signal interface defining a plurality of direct signal paths between the handling apparatus and the pin electronics assembly.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.