Block interleave circuit
US6476738B1 · kind B1 · utility
7Cited by
6References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Dec 21, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2703
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
By a shift register, n×d bits of data input Din are converted into parallel signals and latched by a register. A shift register is loaded with the parallel signals latched to the register when a data load signal is at high level and converts the loaded parallel signals into serial signals and outputs the serial signals as output data Dout when the data load signal is at low level. Therefore, connection between the register and the shift register is set such that a time-sequential order of the input data Din can be switched and accordingly, block interleaving can be carried out without using storages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.