Semiconductor memory device having different data rates in read operation and write operation
US6477110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 17, 2001 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Aug 17, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device and a system using the semiconductor memory device can perform a data sampling operation safely without a phase synchronization device such as delay locked loop (DLL) or phase locked loop (PLL), wherein the semiconductor memory device incorporates a strobe signal, which is synchronized with a data signal, both traversing similar-length paths between a memory device and a memory controller. In a read operation, the semiconductor memory device generates a first strobe signal synchronized with a read data signal, whereby a read data signal is outputted at both a rising and a falling edge of a strobe signal. In a write operation, a second strobe signal is generated whereby only a single edge is used to generate a write data signal, thereby allowing sufficient time for a data sampling operation to occur and thus operating at half the speed of a read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.