Fast operating multiplexer
US6477186B1 · kind B1 · utility
35Cited by
3References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 29, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jul 29, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04J3/047
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a multiplexer, flip-flops for timing control are interposed between a control signal generating circuit and a four-to-one selector, and a flip-flop is interposed between a quarter divider and flip-flops provided for data input. A sum of delay times of the quarter divider and the control signal generating circuit and a setup time of the flip-flops for timing control is merely required to fall within one clock cycle, and therefore an operation speed can be high.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.