Sampling control loop for a receiver for digitally transmitted signals
US6477215B1 · kind B1 · utility
7Cited by
3References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 25, 1998 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Sep 25, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0062
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
To optimize the sampling of individual symbols (S0 to S3), a sampling control loop (1) for a circuit (2) for receiving digitally transmitted signals (s) is connected to a timing error detector (3) which determines the respective timing error values (td). To improve the control action of the sampling control loop (1), an evaluating device (11) determines a reliability value (v) from signals (I, Q; Is, Qs; sb, sp; sr) of the receiving circuit (2) and controls the sampling control loop (1) in accordance with the reliability value (v).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.