Device and method for performing a leading zero determination on an operand
US6477552B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Nov 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/74
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device for performing a consecutive clear bits count on an operand with an offset includes a plurality of logic circuits, each associated with a prioritized portion of the operand. Each logic circuit activates an all-zero signal when its respective portion of the operand consists of all zeros, performs a leading zero count on its respective portion of the operand, and generates a leading zero signal by offsetting its leading zero count with a first portion of the offset. Also, a priority encoder generates a signal encoding the priority of the highest priority inactive all-zero signal, and muxes select first and second portions of the leading zero signal associated with the highest priority inactive all-zero signal as a first portion of the consecutive clear bits count and a carryout selector signal, respectively, in accordance with the priority encoded signal. Further, adders generate a no-carryout signal by offsetting the priority encoded signal with a second portion of the offset, and generate a carryout signal by offsetting the priority encoded signal with the second portion of the offset and adding one. A mux then selects one of the no-carryout and carryout signals as a secon…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.