Memory controller arbitrating RAS, CAS and bank precharge signals
US6477598B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 20, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Jan 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller for controlling a multiple bank DRAM comprises a pool/queue state machine, a plurality of transaction processor state machines, a command arbitor and a plurality of bank state machines, preferably one bank state machine for each bank in the DRAM. As transactions are received by the controller, they are allocated by the pool/queue state machine to one of the transaction processor state machines. The receiving transaction processor state machine first checks if the memory bank corresponding to the read/write address is available. Once the bank is available, the transaction processor state machine then sends RAS and CAS requests request to the arbitor. The arbitor receives this request and arbitrates between it and other pending requests (both CAS and RAS requests from the other transaction processor state machines and precharge requests from the bank state machines). When the bank state machine corresponding to the bank activated by a particular RAS command detects that RAS command on the arbitor output, it becomes active, and eventually issue a precharge command to the arbitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.