Hierarchical row activation method for banking control in multi-bank DRAM
US6477630B2 · kind B2 · utility
3Cited by
9References
12Claims
0Family size
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Key dates
| Filing date | Feb 24, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Feb 24, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4087
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory structure comprises a plurality of banks (each of the banks including a plurality of blocks) a plurality of timing critical address lines connected to all of the blocks in respective ones of the banks (a number of the critical address lines being equal to a number of the banks), and a plurality of dedicated address lines connected to respective ones of the blocks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.