Logic equivalence leveraged placement and routing of an IC design
US6477688B1 · kind B1 · utility
Inventor
Key dates
| Filing date | Dec 22, 1999 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Dec 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/327
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
At least one EDA tool is provided with first and second plurality of programming instructions. The first plurality of programming instructions are designed to determine equivalent logic in an IC design, and the second plurality of programming instructions are designed to place and route the IC design. The place and route operation includes performance of at least one place and route operation selected from a group of place and route operations consisting of choosing coupling assignments for nets and logically equivalent input pins of the IC design, and choosing coupling assignments for logically equivalent output pins and loads of the IC design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.