In-place repeater insertion methodology for over-the-block routed integrated circuits
US6477690B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 18, 2000 |
| Grant date | Nov 5, 2002 |
| Priority date | — |
| Expiry date | Feb 18, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and system for performing in-place insertion of interconnect repeaters in an integrated circuit is presented. The integrated circuit comprises a silicon layer and at least one interconnect layer layered over said silicon layer. Metal tracks are reserved on each of the interconnect layers in predefined repeater areas. The interconnects are then routed to pass over the pre-defined repeater areas. For each interconnect, a set of optimal constrained repeater locations are calculated, as defined by the optimal number and locations of repeaters along the interconnect route and as constrained by a set of legal repeater locations associated with the interconnect and which will result in acceptable timing criteria. For each calculated optimal constrained repeater location, a repeater is stitched in-place through the reserved metal tracks of the intervening layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.