Current-limiting device
US6479882B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2000 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Dec 18, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02H9/02
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The current-limiting device 1 includes a silicon substrate 2 having surfaces opposite to each other, and two electrodes 3 deposited respectively on the opposite surfaces of the silicon substrate. The silicon substrate 2 is of a three-layered structure including an N− layer 4 of a low impurity density and an N+ layers 5 of a high impurity density formed respectively on opposite surfaces of the N− layer 4. The electrodes 3, are deposited on an outer surface of each of the N+ layers 5 remote from the N− layer 4. The constant current substantially flows in the current-limiting device 1 if the applied voltage is higher than a predetermined value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.