Transmitter circuit comprising timing deskewing means
US6480021B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Nov 6, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0292
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present invention relates generally to the transmission of digital data. More particularly, the invention relates to a high-speed data transmission between integral circuits (ICs) or chips.A data transmission means for high-speed transmission of digital data is proposed, the data transmission means comprising:at least one driver for driving a transmission line; anda timing deskewing means connected thereto, whereinthe timing deskewing means comprisesa storage means for recording and storing information on skew caused by inter-symbol interference and cross-talk influence in the transmission line, for at least one data pattern transmitted through the transmission line; andan adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate for the above skew.The present invention allows to reduce the skew of signals at the end of a transmission line so as to compensate for the effects of cross-talk and various signal reflections, settling time influence, or other kind of inter-symbol interference like fre…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.