Content addressable memory cell
US6480406B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 22, 2001 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Aug 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Architecture, circuitry, and methods are provided for producing a content addressable memory (CAM). The CAM includes one or more CAM cells arranged in an array. Each CAM cell is symmetrical about its x- and y-axis to form rows and columns of the array. Additionally, each CAM cell can use either SRAM or DRAM storage cells implemented in either a binary or ternary arrangement. If the CAM cell is a ternary SRAM design, then the cell size is no more than 4 microns by 1-½ microns, assuming a 0.15 micron critical dimension. Critical dimension is noted as the smallest resolvable size for the particular process being employed. The CAM cell utilizes a selection circuitry that will disable the compare circuit during times when a compare operation is not being performed. This will ensure the compare circuit will not consume power during, for example, a read or write operation. Each CAM cell uses no more than eight conductors per cell, wherein the conductors are of minimum width and pitch arranged co-planar on a single metal layer. Another metal layer utilizes local interconnects and a pair of conductors which carry the differential bit lines and compare lines. The local interconnects d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.