Floating-point and integer multiply-add and multiply-accumulate
US6480872B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 21, 1999 |
| Grant date | Nov 12, 2002 |
| Priority date | — |
| Expiry date | Jan 21, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and a device including, in one embodiment, a multiply array and at least one adder to perform a floating-point multiplication followed by an addition when operands are in floating-point format. The device is also configured to perform an integer multiplication followed by an accumulation when operands are in integer format. The device is further configured to perform a floating-point multiply-add or an integer multiply-accumulation in response to control signals. In another embodiment, the device contains an adder and the adder is capable of performing a floating-point addition and an integer accumulation. The adder is configured to be extra wide to reduce operand misalignment. Moreover, the device stalls the process in response to operand misalignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.